AMD Launches Instinct MI400 Chips and Helios Rack, Challenges Nvidia

AMD has moved from roadmap slides to actual hardware. At the two-day Advancing AI 2026 conference at San Francisco's Moscone Center, CEO Lisa Su presented on July 23 the first details of mass production for the Instinct MI400 accelerator family, the Helios rack system, and the EPYC Venice server processor, AMD's first x86 chip built on TSMC's 2-nanometer process.

A new Instinct chip family

The Instinct MI400 is AMD's first generation of accelerators designed from the outset for rack-scale deployment rather than as standalone cards. The MI450, the most capable variant in the lineup, offers 432 GB of HBM4 memory and bandwidth of around 19.6 TB per second, reaching 40 PFLOPs in FP4 compute. It also delivers scale-out bandwidth of 300 GB per second, key for linking multiple chips into a single training cluster.

AMD directly compares these specs to Nvidia's Vera Rubin platform, pointing to an edge in memory capacity and chip-to-chip bandwidth. That marks a shift in tone from earlier Instinct generations, where AMD positioned itself as the cheaper alternative rather than a direct rival on specs.

Helios rack as the unit of sale

Instead of selling standalone accelerators, AMD is increasingly betting on Helios, a complete rack combining Instinct chips, EPYC processors, and AMD Pensando networking into one ready-to-deploy system. The double-wide Helios version, slated for the third quarter of 2026, is meant to deliver up to 3 exaflops of AI compute and 31 TB of HBM4 memory in a single cabinet.

We are entering the era of yottascale computing, driven by unprecedented growth in both training and inference. - Lisa Su, CEO of AMD

Su called Helios "the best AI rack in the world" and described it as "the blueprint for yottascale computing," referring to future data centers with capacity measured in yottaflops. That's rhetoric AMD has consistently repeated since January, when Helios was first teased at CES 2026.

EPYC Venice and the bet on x86

Alongside the accelerators, AMD showed off the fifth-generation EPYC Venice server processors, the company's first x86 chip built on TSMC's 2-nanometer process. By AMD's own internal estimates, the new platform delivers up to 330 percent higher performance per rack compared with rival Nvidia Vera processors, which power the green chipmaker's competing rack systems.

That matters because AMD has for years treated general-purpose processors as a complement to its accelerator lineup, while Nvidia has recently started designing its own CPUs to pair with its GPUs. EPYC Venice is meant as a response signaling that AMD won't cede this segment without a fight.

Contracts for gigawatts of capacity

The most concrete evidence that MI400 and Helios are more than announcements comes from customer contracts. AMD confirmed that OpenAI and Meta have together reserved 12 gigawatts of compute capacity based on its chips, with Microsoft Azure and Oracle named as the first cloud operators deploying Helios. A previously announced deal with OpenAI calls for 6 gigawatts of capacity under a multi-year contract, starting with an initial 1-gigawatt tranche of MI450-class accelerators in the second half of 2026.

We are excited to work with OpenAI to deliver AI compute at massive scale. This partnership brings together the best of AMD and OpenAI, creating a win-win and supporting the most ambitious AI infrastructure build-out in the world. - Lisa Su, CEO of AMD

Rising orders are already showing up in the financial results. AMD's data center segment grew 57 percent year over year in the first quarter of 2026, to $5.8 billion, while total company revenue reached $10.3 billion, up 38 percent. The second-quarter guidance calls for revenue of around $11.2 billion, a roughly 46 percent year-over-year increase.

What it means for the market

For Polish companies and system integrators, the direct impact of this launch is limited, since Helios and MI400 are going first to hyperscalers like Microsoft, Oracle, and Meta rather than to local data centers. Indirectly, though, AMD's competition with Nvidia affects the pricing and availability of cloud compute, which Polish AI startups and companies building their own models also rely on.

The roadmap already stretches to 2027, when the Instinct MI500 is due to debut on the CDNA 6 architecture, also on a 2-nanometer process and with HBM4E memory. AMD is promising a thousand-fold performance increase for this generation over the earlier MI300X chips, though such claims made at the launch of successive AI chip generations should be treated as marketing targets rather than measured results.